single-rb.php

JRM Vol.17 No.4 pp. 395-400
doi: 10.20965/jrm.2005.p0395
(2005)

Paper:

A 3.7×3.7mm² 310.9mW 105.2msec 512×512-Pixel Phase-Only Correlation Processor

Naoto Miyamoto*, Koji Kotani*, and Tadahiro Ohmi**

*Department of Electronic Engineering, Graduate School of Engineering, Tohoku University, 6-6-05 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan

**New Industry Creation Hatchery Center, Tohoku University, 6-6-10 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan

Received:
November 28, 2004
Accepted:
February 19, 2005
Published:
August 20, 2005
Keywords:
image recognition, phase-only correlation, dynamically reconfigurable ALU, FFT, IFFT
Abstract

The image recognition processor we propose implements the phase-only correlation (POC) algorithm. Its arithmetic-logic unit (ALU) is dynamically reconfigurable to any necessary circuitry for POC by itself. 2-stage cached-memory architecture (CMA) is developed so that high-radix batch processing is possible. By transforming the original POC algorithm into the optimum form for the dynamically reconfigurable ALU and 2-stage CMA, the proposed processor executes two-dimensional 512×512 pixel image recognition within 105.2msec and 310.9mW at 80MHz in an area 3.7×3.7mm². Its power consumption is over 11.3 times lower than that of previously reported work.

Cite this article as:
Naoto Miyamoto, Koji Kotani, and Tadahiro Ohmi, “A 3.7×3.7mm² 310.9mW 105.2msec 512×512-Pixel Phase-Only Correlation Processor,” J. Robot. Mechatron., Vol.17, No.4, pp. 395-400, 2005.
Data files:
References
  1. [1] M. Morikawa, A. Katsumata, and K. Kobayashi, “An image processor implementing algorithms using characteristics of phase spectrum of two-dimensional Fourier transformation,” ISIE’99, pp. 1208-1213, 1999
  2. [2] K. Kobayashi, H. Nakajima, T. Aoki, M. Kawamata, and T. Higuchi, “Principles of Phase Only Correlation and Its Applications,” The Institute of Image Information and Television Engineers (ITE) Technical Report, Vol.20, No.41, pp. 1-6, MIP’ 96-53, NIM’ 96-75, 1996 (in Japanese).
  3. [3] K. Maruo, M. Ichikawa, N. Miyamoto, L. Karnan, T. Yamaguchi, K. Kotani, and T. Ohmi, “A Dynamically-Reconfigurable Image Recognition Processor,” Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS’04), pp. 151-157, 2004.
  4. [4] J. W. Cooley, and J. W. Tukey, “An algorithm for the machine calculation of complex Fourier series,” Mathematics of Computation, Vol.19, Issue 90, pp. 297-301, 1965.
  5. [5] T. S. Huang, J. W. Burnett, and A. G. Deczky, “The importance of phase in image processing filters,” IEEE Trans. on Acous., Speech and Signal Processing, Vol.ASSP-23, No.6, pp. 529-542, 1975.
  6. [6] L. Karnan, N. Miyamoto, K. Maruo, K. Kotani, and T. Ohmi, “Butterfly-Unit Based Programmable Computation Element Using Merged Module of Multiplication, Division and Square Root,” Extended Abstract of the 2003 International Conference on Solid-State Device and Materials (SSDM2003), pp. 148-149, 2003.
  7. [7] B. M. Baas, “A Low-Power, High-Performance, 1024-Point FFT Processor,” IEEE Journal of Solid-State Circuits, Vol.34, No.3, pp. 380-387, 1999.
  8. [8] N. Miyamoto, L. Karnan, K. Maruo, K. Kotani, and T. Ohmi, “A 100MHz 7.84mm2 31.7msec439mW 512-point 2-dimensional FFT single-chip processor,” IEICE Trans. on Elec., Vol.E87-C, No.4, pp. 502-509, 2004.

*This site is desgined based on HTML5 and CSS3 for modern browsers, e.g. Chrome, Firefox, Safari, Edge, Opera.

Last updated on Jun. 24, 2021