JRM Vol.17 No.4 pp. 395-400
doi: 10.20965/jrm.2005.p0395


A 3.7×3.7mm² 310.9mW 105.2msec 512×512-Pixel Phase-Only Correlation Processor

Naoto Miyamoto*, Koji Kotani*, and Tadahiro Ohmi**

*Department of Electronic Engineering, Graduate School of Engineering, Tohoku University, 6-6-05 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan

**New Industry Creation Hatchery Center, Tohoku University, 6-6-10 Aza-Aoba, Aramaki, Aoba-ku, Sendai 980-8579, Japan

November 28, 2004
February 19, 2005
August 20, 2005
image recognition, phase-only correlation, dynamically reconfigurable ALU, FFT, IFFT
The image recognition processor we propose implements the phase-only correlation (POC) algorithm. Its arithmetic-logic unit (ALU) is dynamically reconfigurable to any necessary circuitry for POC by itself. 2-stage cached-memory architecture (CMA) is developed so that high-radix batch processing is possible. By transforming the original POC algorithm into the optimum form for the dynamically reconfigurable ALU and 2-stage CMA, the proposed processor executes two-dimensional 512×512 pixel image recognition within 105.2msec and 310.9mW at 80MHz in an area 3.7×3.7mm². Its power consumption is over 11.3 times lower than that of previously reported work.
Cite this article as:
N. Miyamoto, K. Kotani, and T. Ohmi, “A 3.7×3.7mm² 310.9mW 105.2msec 512×512-Pixel Phase-Only Correlation Processor,” J. Robot. Mechatron., Vol.17 No.4, pp. 395-400, 2005.
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Last updated on Jul. 19, 2024