Report:
Sophisticated CMP Technology with In-Line Optical-Thickness Verification for Shallow-Trench-Isolation Formation in GAAFETs with Multilayered Si/SiGe Superlattices
Yuji Kasashima
, Takashi Matsukawa
, Atsushi Yagishita, and Yoshihiro Hayashi

Semiconductor Frontier Research Center, National Institute of Advanced Industrial Science and Technology (AIST)
16-1 Onogawa, Tsukuba, Ibaraki 305-8569, Japan
Corresponding author
A sophisticated chemical mechanical polishing (CMP) technology with in-line optical-thickness verification was developed for shallow-trench isolation formation in gate-all-around field-effect transistors with a multilayered Si/SiGe superlattice. The CMP tools were equipped with in-line optical critical dimension (OCD) measurement and a torque current monitor of the CMP turn-table motor for endpoint detection (EPD). In this study, model-based OCD fitting was applied to estimate the thicknesses of complex multilayered films: a SiN stopper on a thin SiO2 buffer layer over a Si/SiGe/Si/SiGe/Si/SiGe superlattice epitaxially grown on a Si substrate. Immediately after the CMP with the electrical EPD and the in-line OCD measurement, the over-polished thickness of the SiN stopper was within 3 nm on the fin-patterned Si/SiGe superlattice despite the change in the SiO2–CMP rate during continuous wafer processing. This nondestructive CMP control method improves the efficiency and quality of the CMP process in GAAFET fabrication.
Cross-sectional TEM images after STI SiO2 CMP
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