Top > JRM > A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip f ...

single-rb.php

JRM Vol.17 No.4 pp. 463-468
doi: 10.20965/jrm.2005.p0463
(2005)

Paper:

Views over last 60 days: 309

A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors

Mitsuru Shiozaki, Toru Mukai, Masahiro Ono,
Mamoru Sasaki, and Atsushi Iwata

Hiroshima University, 1-3-1 Kagamiyama, Higashihiroshima-shi, Hiroshima 739-8530, Japan

Received:
November 30, 2004
Accepted:
February 19, 2005
Published:
August 20, 2005
Creative Commons License
Keywords:
CDMA, serial communication, real-time, synchronization technique
Abstract
Intelligent robot control using multiprocessors, sensors, and actuators requires real-time flexible networks for communicating various types of real-time data, e.g., sensing data and interrupt signals. Furthermore, serial data transfer is required for implementing the network using a few wiring lines. To meet these requirements, we propose a CDMA serial communication interface utilizing novel two-step synchronization. The transmitter and receiver chip fabricated with 0.25μm digital CMOS technology achieved 2.7Gcps (chips per second) and 7-multiplex communication. The experimental interface board was developed for demonstrating flexible transfer of multiimage data by installing CDMA chips in addition to an FPGA.
Cite this article as:
M. Shiozaki, T. Mukai, M. Ono, M. Sasaki, and A. Iwata, “A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors,” J. Robot. Mechatron., Vol.17 No.4, pp. 463-468, 2005.
Data files:
References
  1. [1] N. Yamasaki, “Design and Implementation of Real-time Communication Responsive Link for Distributed Control,” Information Processing Society of Japan Journal, Vol.45, No.SIG 3(ACS 5), pp. 50-63, Mar. 2004.
  2. [2] M. Shiozaki et al., “CDMA Communication Chips for Highly Flexible Robot Brain,” SICE System Integration Division Annual Conference, 1D3-5, p. 76, Dec. 2003.
  3. [3] R. Yoshimura et al., “DS-CDMA Wired Bus with Simple Interconnection Topology for Parallel Processing System LSIs,” ISSCC Digest of Tech. Papers, pp. 370-371, Feb. 2000.
  4. [4] Z. Xu et al., “A 2.7Gb/s CDMA-Interconnect Transceiver Chip Set with Multi-Level Signal Data Recovery for Re-configurable VLSI System,” ISSCC Digest of Technical Papers, pp. 82-83, Feb. 2003.
  5. [5] M. Shiozaki et al., “A 2Gbps and 7-multiplexing CDMA Serial Receiver Chip for Highly Flexible Robot Control System,” Symposium on VLSI Circuits, Digest of Technical Paper, pp. 194-197, Jun. 2004.
  6. [6] M. Shiozaki et al., “A 2Gbps and 7-multiplexing CDMA Serial Receiver Chip for Highly Flexible Robot Control System,” Technical Report of IEICE, SDM2004-136, ICD2004-78, pp. 97-102, 2004.

Creative Commons License  This article is published under a Creative Commons Attribution-NoDerivatives 4.0 Internationa License.

Copyright© 2005 by Fuji Technology Press Ltd. and Japan Society of Mechanical Engineers. All right reserved.

*This site is desgined based on HTML5 and CSS3 for modern browsers, e.g. Chrome, Firefox, Safari, Edge, Opera.

Last updated on May. 24, 2023