Design and Implementation of the Multimedia Operation Mechanism for Responsive Multithreaded Processor
Tsutomu Itou*, and Nobuyuki Yamasaki**
*School of Science for Open and Environmental Systems, Keio University, Yokohama, Kanagawa 223-8522, Japan
**Department of Information and Computer Science, Keio University, Yokohama, Kanagawa 223-8522, Japan
Responsive Multithreaded (RMT) Processor is designed for distributed real-time systems. This paper focuses on the multimedia processing architecture of RMT Processor. Multimedia processing requires high-throughput calculation for bulky data processing. RMT Processor architecture is based on eight-way prioritized simultaneous multithreading, which executes each thread in order of priority. Since the priority of hard real-time threads is higher than that of multimedia processing threads, instruction issue slots used by the multimedia processing threads are few in RMT Processor when hard real-time threads are executed simultaneously. Therefore multimedia processing threads need to utilize instruction issue slots effectively to achieve high performance. We have designed a novel vector operation mechanism to process multimedia data efficiently in parallel. Because the same instructions are iterated in multimedia processing, the compound operation mechanism is designed to calculate more data per instruction in multimedia processing.
-  N. Yamasaki, “Design concept of responsive multithreaded processor for distributed real-time control,” Journal of Robotics and Mechatronics, Vol.16, No.2, pp. 194-199, 2004.
-  N. Yamasaki, “Design and implementation of responsive processor for parallel/distributed control and its development environment,” Journal of Robotics and Mechatronics, Vol.13, No.2, pp. 125-133, 2001.
-  S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, R. L. Stamm, and D. M. Tullsen, “Simultaneous multithreading: A platform for nextgeneration processors,” IEEE Micro, Vol.17, No.5, pp. 12-19, 1997.
-  D. M. Tullsen, S. J. Eggers, and H. M. Levy, “Simultaneous multithreading: Maximizing on-chip parallelism,” In Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995.
-  M. Utiyama, T. Itou, J. Sato, N. Yamasaki, and Y. Anzai, “A new processor architecture for real-time systems,” In IFAC Conference on New Technologies for Computer Control 2001, 2001.
-  H. Oehring, U. Sigmund, and T. Ungerer, “Simultaneous multithreading and multimedia,” In MTEAC 99, 1999.
-  S. K. Raman, V. Pentkovski, and J. Keshave, “Implementing Streaming SIMD Extensions on the PentiumIII Processor,” IEEE Micro, Vol.20, No.4, pp. 47-57, 2000.
-  K. Diefendorff, P. K. Dubey, R. Hochsprung, and H. Scales, “Altivec Extension to PowerPC Accelerates Media Processing,” IEEE Micro, Vol.20, No.2, pp. 85-95, 2000.
-  R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, and A. Seznec, “Tarantula: A Vector Extension to the Alpha Architecture,” In Proceedings of the 29th Annual International Symposium of Computer Architecture, pp. 281-292, May 2002.
This article is published under a Creative Commons Attribution-NoDerivatives 4.0 Internationa License.
Copyright© 2005 by Fuji Technology Press Ltd. and Japan Society of Mechanical Engineers. All right reserved.