single-rb.php

JRM Vol.17 No.4 pp. 410-419
doi: 10.20965/jrm.2005.p0410
(2005)

Paper:

Real-Time Shape Recognition Using a Pixel-Parallel Processor

Takashi Komuro, Yoshiki Senjo, Kiyohiro Sogen,
Shingo Kagami, and Masatoshi Ishikawa

Department of Information Physics and Computing, Graduate School of Information Science and Technology, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan

Received:
November 25, 2004
Accepted:
March 22, 2005
Published:
August 20, 2005
Keywords:
real-time vision, parallel processing, VLSI, vision chip
Abstract

We propose a method to realize robust real-time shape recognition against noise and occlusion by using information of an entire image, and by performing image processing in a pixel parallel manner. The evaluation by simulation showed that the proposed method was effective for images with noise or partially occluded images. We implemented the algorithm to a vision chip which performs pixel-parallel processing and confirmed real-time operation. We also estimated the performance of the method on an ideal processor.

References
  1. [1] S. Yamane, M. Izumi, and K. Fukunaga, “A Method of Model-Based Pose Estimation,” IEICE Transactions on Information and Systems, pt.2 (Japanese Edition), Vol.J79-D-II, No.2, pp. 165-173, 1996 (in Japanese).
  2. [2] F. Toyama, K. Shoji, and J. Miyamichi, “Pose Estimation from a Line Drawing Using Genetic Algorithm,” IEICE Transactions on Information and Systems, pt.2 (Japanese Edition), Vol.J81-D-II, No.7, pp. 1584-1590, 1998 (in Japanese).
  3. [3] M. Ishikawa, and T. Komuro, “Digital Vision Chips and High-Speed Vision Systems,” 2001 Symposium on VLSI Circuits Digest of Technical Papers, pp. 1-4, 2001.
  4. [4] E. S. Gayles, T. P. Kelliher, R. M. Owens, and M. J. Irwin, “The Design of MGAP-2: A Micro-Grained Massively Parallel Array,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.8, No.6, pp. 709-716, 2000.
  5. [5] J. C. Gealow, F. P. Herrmann, L. T. Hsu, and C. G. Sodini, “System Design for Pixel Parallel Image Processing,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.4, No.1, pp. 32-41, 1996.
  6. [6] I. Ishii, and M. Ishikawa, “Matching Algorithms for Massively Parallel Vision,” Technical Report of the Institute of Electronics, Information and Communication Engineers, PRU95-70, Vol.95, No.165, pp. 121-126, 1995 (in Japanese).
  7. [7] T. Komuro, S, Kagami, and M, Ishikawa, “A Dynamically Reconfigurable SIMD Processor for a Vision Chip,” IEEE Journal of Solid-State Circuits, Vol.39, No.1, pp. 265-268, 2004.
  8. [8] S. Kagami, T. Komuro, and M. Ishikawa, “A High-Speed Vision System with In-Pixel Programmable ADCs and PEs for Real-Time Visual Sensing,” Proc. 8th IEEE International Workshop on Advanced Motion Control, pp. 439-443, 2004.

*This site is desgined based on HTML5 and CSS3 for modern browsers, e.g. Chrome, Firefox, Safari, Edge, IE9,10,11, Opera.

Last updated on Jan. 23, 2018