Responsive Multithreaded Processor for Distributed Real-Time Systems
Department of Information and Computer Science, Faculty of Science and Technology, Keio University, 3-14-1 Hiyoshi, Kouhoku-ku, Yokohama 223-8522, Japan
The Responsive MultiThreaded (RMT) Processor is a system LSI that integrates almost all functions for parallel/distributed real-time systems including robots, intelligent rooms/buildings, ubiquitous computing systems, and amusement systems. Concretely, the RMT Processor integrates real-time processing (RMT Processing Unit), real-time communication (Responsive Link II), computer I/O peripherals (DDR SDRAM I/Fs, DMAC, PCI-X, USB2.0, IEEE1394, etc.), and control I/O peripherals (PWM generators, pulse counters, etc.). The RMT Processor, with a design rule of 0.13μm CMOS Cu 1P8M and a die size 10.0mm square, was fabricated by TSMC. The RMT Processing Unit (RMT PU) executes eight prioritized threads simultaneously using fine-grained multithreading based on priority, called the RMT architecture. Priority of real-time systems is introduced into all functional units, including cache, fetch, and execution, so the RMT PU guarantees real-time execution of prioritized threads. If resource conflicts occur at functional units, higher priority threads overtake lower priority threads. Flexible powerful vector operation units for multimedia processing are also designed. System designers use on-chip functions easily by connecting required I/Os to this chip and the designers realize distributed control by connecting several RMT Processors with their own functions via Responsive Link II.
-  N. Yamasaki, “Design Concept of Responsive Multithreaded Processor for Distributed Real-Time Control,” Journal of Robotics and Mechatronics, Vol.16, No.2, pp. 194-199, April 2004.
-  N. Yamasaki, “Responsive Processor for Parallel/Distributed Real-Time Control,” International Conference on Intelligent Robots and Systems, pp. 1238-1244, November 2001.
-  http://www.itscj.ipsj.or.jp/ipsj-ts/02-06/toc.htm.
-  S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, R. L. Stamm, and D. M. Tullsen, “Simultaneous multithreading: A platform for nextgeneration processors,” IEEE Micro, Vol.17, No.5, pp. 12-19, 1997.
-  D. M. Tullsen, S. J. Eggers, J. S. Emer, H. M. Levy, J. L. Lo, and R. L. Stamm, “Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,” In Proceedings of the 23rd Annual International Symposium on Computer Architecture, 1996.
-  J. Kreuzinger, A. Schulz, M. Preffer, T. Ungerer, and U. Brinkschutle, “Real-Time Scheduling on Multithread Processor,” Real Time Computing Systems and Applications (RTCSA), pp. 155-159, 2000.
-  S. E. Raasch, and S. K. Reinhardt, “Applications of Thread Prioritization in SMT Processors,” Workshop on Multithreaded Execution, Architecture and Compilation (MTEAC), 1999.
-  R. Jain, C. J. Hughes, and S. V. Adve, “Soft Real-Time Scheduling on Simultaneous Multithreaded Processors,” In Proceeding of the 23rd IEEE Real-Time Systems Symposium (RTSS), 2002.
-  J. W. S. Liu, “Real-Time Systems,” Prentice Hall, 2000.
-  http://www.ny.ics.keio.ac.jp/.
This article is published under a Creative Commons Attribution-NoDerivatives 4.0 Internationa License.
Copyright© 2005 by Fuji Technology Press Ltd. and Japan Society of Mechanical Engineers. All right reserved.