Coordinate Transformation VLSI Processor for Redundant Manipulator Control
Yoshichika Fujioka*, Michitaka Kameyama*, and Tatsuo Higuchi**
* Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University
** Department of System Information Sciences, Graduate School of Information Sciences, Tohoku University, Aoba, Aramaki, Aoba-ku, Sendai, Miyagi, 980-77 Japan
A computationally efficient algorithm called ‘Subsequent-division algorithm’ is presented to develop a special-purpose VLSI processor for differential inverse kinematics computation of redundant manipulators. Because the computation is performed in a feedback loop, not only throughput but also absolute delay time must be considered as performance factor An architecture of a reconfigurable parallel VLSI processor is proposed to improve the utilized ratio of the multipliers contained in processor elements (PEs). In each PE, switching hardware is used to change the connections between the multipliers and the adders, so that we can reconfigure the multiply-adders having desired numbers of multipliers. The chip evaluation based on Iμm CMOS design rule shows that the total delay time for a 12 degrees-of-freedom (DOF) redundant manipulator becomes about 13μsec which is about ninety times faster than that of a parallel processor approach using general-purpose microprocessors.