Next-Generation Intelligent Integrated Systems Based on Multiple-Valued Digital  Processing

Michitaka Kameyama

doi:10.20965/jrm.1994.p0120

single-rb.php

« previous

JRM Vol.6 No.2 pp. 120-123

doi: 10.20965/jrm.1994.p0120

(1994)

Review:

Views over last 60 days: 341

Next-Generation Intelligent Integrated Systems Based on Multiple-Valued Digital Processing

Michitaka Kameyama

Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University, Aoba, Aramaki, Aoba-ku, Sendai, Miyagai, 980-77 Japan

Received:

December 20, 1993

Accepted:

December 25, 1993

Published:

April 20, 1994

Keywords:

Multiple-valued integrated circuits, Intelligent integrated systems, VLSI processor, Highly parallel arithmetic and logic circuits, Multiple-valued coding

Abstract

Cite this article as:

Michitaka Kameyama, “Next-Generation Intelligent Integrated Systems Based on Multiple-Valued Digital Processing,” J. Robot. Mechatron., Vol.6, No.2, pp. 120-123, 1994.

Data files:

This article is published under a Creative Commons Attribution-NoDerivatives 4.0 International License.