JACIII Vol.18 No.5 pp. 849-855
doi: 10.20965/jaciii.2014.p0849


A Study on Computational Time Reduction of Road Obstacle Detection by Parallel Image Processor

Yutaro Okamoto, Chinthaka Premachandra, and Kiyotaka Kato

Department of Electrical Engineering, Graduate School of Engineering, Tokyo University of Science,

May 4, 2014
June 29, 2014
September 20, 2014
computational time reduction, obstacle detection, parallel image processor, image sample variance, discriminant analysis
Automatic road obstacle detection is one of the significant problem in Intelligent Transport Systems (ITS). Many studies have been conducted for this interesting problem by using on-vehicle cameras. However, those methods still needs a dozens of milliseconds for image processing. To develop the quick obstacle avoidance devices for vehicles, further computational time reduction is expected. Furthermore, regarding the applications, compact hardware is also expected for implementation. Thus, we study on computational time reduction of the road obstacle detection by using a small-type parallel image processor. Here, computational time is reduced by developing an obstacle detection algorithm which is appropriated to parallel processing concept of that hardware. According to the experimental evaluation of the new proposal, we could limit computational time for eleven milliseconds with a good obstacle detection performance.
Cite this article as:
Y. Okamoto, C. Premachandra, and K. Kato, “A Study on Computational Time Reduction of Road Obstacle Detection by Parallel Image Processor,” J. Adv. Comput. Intell. Intell. Inform., Vol.18 No.5, pp. 849-855, 2014.
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