Simulation of Dislocation Accumulation in Impurity Doped-ULSI Cells and Electric Characteristic Evaluations
Michihiro Sato*,† and Yosuke Takahashi**
*Department of Mechanical Engineering, Kitami Institute of Technology
165 Koen-cho, Kitami, Hokkaido 090-8507, Japan
1-7-2 Otemachi, Chiyoda-ku, Tokyo 100-0004, Japan
The performance of semiconductor devices has improved on introducing increasing refinements to the structures of these devices. This has created various problems at the atomic level. In particular, the presence of dislocations, a type of crystallographic defect, within semiconductor devices poses a major problem. Dislocations accumulated within the device obstruct the movement of electrons and adversely affect the electrical characteristics of the device. However, previous investigations have not sufficiently clarified the relationship between accumulated dislocations and the electrical characteristics of a semiconductor. In this study, we focus on dislocations produced in the fabrication of an impurity-doped ultra-large-scale integration (ULSI) device and, based on a crystal plasticity analysis, perform a simulation of the accumulation of dislocations within the device during the cooling process. We establish an analytical system by which the obtained information on dislocations is applied to a device simulator, in order to evaluate the electrical characteristics by considering the accumulation of dislocations. We investigate the effects that dislocation density and density distribution have on the characteristic current-voltage curve of the device.
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