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JRM Vol.17 No.4 pp. 378-386
doi: 10.20965/jrm.2005.p0378
(2005)

Paper:

A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation

Teppei Nakano*, Takashi Morie*, Makoto Nagata**,
and Atsushi Iwata***

*Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology, Hibikino, Wakamatsu-ku, Kitakyushu 808-0196, Japan

**Department of Computer and Systems Engineering, Kobe University, Nada-ku, Kobe 657-8501, Japan

***Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashi-Hiroshima 739-8526, Japan

Received:
December 14, 2004
Accepted:
February 19, 2005
Published:
August 20, 2005
Keywords:
cellular-automaton, region extraction, labeling, pixel-parallel operation, FPGA implementation
Abstract

This paper proposes a new region extraction algorithm and its digital LSI architecture based on cellular-automaton operation for very fast image processing. The algorithm sequentially extracts each region defined by a closed boundary. From digital logic simulation using Verilog-HDL, the proposed circuit with pixel-parallel operation can operate 100 times faster than serial labeling for a 100×100-pixel image. We implemented the proposed circuit in an FPGA for 30×30-pixel image processing. In an experiment with the FPGA, five regions are successfully extracted one by one within 6μs at a clock frequency of 25MHz.

Cite this article as:
Teppei Nakano, Takashi Morie, Makoto Nagata, and
and Atsushi Iwata, “A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation,” J. Robot. Mechatron., Vol.17, No.4, pp. 378-386, 2005.
Data files:
References
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Last updated on Sep. 19, 2021