A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation
Teppei Nakano*, Takashi Morie*, Makoto Nagata**,
and Atsushi Iwata***
*Graduate School of Life Science and Systems Engineering, Kyushu Institute of Technology, Hibikino, Wakamatsu-ku, Kitakyushu 808-0196, Japan
**Department of Computer and Systems Engineering, Kobe University, Nada-ku, Kobe 657-8501, Japan
***Graduate School of Advanced Sciences of Matter, Hiroshima University, Higashi-Hiroshima 739-8526, Japan
This paper proposes a new region extraction algorithm and its digital LSI architecture based on cellular-automaton operation for very fast image processing. The algorithm sequentially extracts each region defined by a closed boundary. From digital logic simulation using Verilog-HDL, the proposed circuit with pixel-parallel operation can operate 100 times faster than serial labeling for a 100×100-pixel image. We implemented the proposed circuit in an FPGA for 30×30-pixel image processing. In an experiment with the FPGA, five regions are successfully extracted one by one within 6μs at a clock frequency of 25MHz.
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