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JRM Vol.13 No.2 pp. 125-133
doi: 10.20965/jrm.2001.p0125
(2001)

Paper:

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Design and Implementation of Responsive Processor for Parallel/Distributed Control and Its Development Environments

Nobuyuki Yamasaki*,**

*Keio University, 3-14-1, Hiyoshi, Kohoku-ku, Yokohama, Kanagawa 223-8522, Japan

**National Institute Advanced Industrial Science and Technology, 1-1-1, Umezono, Tsukuba, Ibaraki 305-8568, Japan

Received:
October 10, 2000
Accepted:
November 7, 2000
Published:
April 20, 2001
Creative Commons License
Keywords:
responsive processor, parallel/distributed control, real-time, system-on-a-chip
Abstract

In this paper, Responsive Processor for parallel/distributed real-time processing, which can control various electronic control systems, is designed and implemented. Responsive Processor is integrates many functions into an ASIC chip, such as a RISC processing core (SPARC), Responsive Links that realize realtime communication, many peripheral functions including SDRMI/Fs, DMAC, PCI, USB, SIO, PIP, timers, pulse counters, PWM generators, A/D converters, D/A converters, etc. Its control boards and development environments are also designed and implemented.

Cite this article as:
N. Yamasaki, “Design and Implementation of Responsive Processor for Parallel/Distributed Control and Its Development Environments,” J. Robot. Mechatron., Vol.13, No.2, pp. 125-133, 2001.
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Creative Commons License  This article is published under a Creative Commons Attribution-NoDerivatives 4.0 Internationa License.

Copyright© 2001 by Fuji Technology Press Ltd. and Japan Society of Mechanical Engineers. All right reserved.

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