Dynamic Scheduling Approaches to Wafer Test Scheduling with Unpredictable Error
Tsubasa Matsuo*, Masahiro Inuiguchi*, and Kenichiro Masunaga**
*Graduate School of Engineering Science, Osaka University, 1-3 Machikaneyama-cho, Toyonaka, Osaka 560-8531, Japan
**Renesas Electronics Co., 2-6-2 Otemachi, Chiyoda-ku, Tokyo 100-0004, Janapn
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