Top > JACIII > Dynamic Scheduling Approaches to Wafer Test Scheduling with Un ...

single-jc.php

JACIII Vol.17 No.4 pp. 526-534
doi: 10.20965/jaciii.2013.p0526
(2013)

Paper:

Views over last 60 days: 526

Dynamic Scheduling Approaches to Wafer Test Scheduling with Unpredictable Error

Tsubasa Matsuo*, Masahiro Inuiguchi*, and Kenichiro Masunaga**

*Graduate School of Engineering Science, Osaka University, 1-3 Machikaneyama-cho, Toyonaka, Osaka 560-8531, Japan

**Renesas Electronics Co., 2-6-2 Otemachi, Chiyoda-ku, Tokyo 100-0004, Janapn

Received:
February 28, 2013
Accepted:
April 12, 2013
Published:
July 20, 2013
Creative Commons License
Keywords:
semiconductor manufacturing, simulation, genetic-based machine learning
Abstract
Scheduling of semiconductor wafer testing processes can be seen as a resource constraint project scheduling problem (RCPSP). However, it includes uncertainties caused by human factors, wafer errors and so on. Because some uncertainties are not simply quantitative, range estimation of the parameters would not be very useful. Considering such uncertainties, finding a good situation-dependent dispatching rule would be more suitable than solving the RCPSP under uncertainties. In this paper we apply the Pitts approach, one of the genetic algorithms, to the situation-dependent dispatching rule acquisition. We compare the obtained rule with the simple dispatching rules and examine the effectiveness and usefulness of the obtained rule in the problems with unpredictable wafer errors.
Cite this article as:
T. Matsuo, M. Inuiguchi, and K. Masunaga, “Dynamic Scheduling Approaches to Wafer Test Scheduling with Unpredictable Error,” J. Adv. Comput. Intell. Intell. Inform., Vol.17 No.4, pp. 526-534, 2013.
Data files:
References
  1. [1] D. Ouelhadj and S. Petrovic, “A Survey of Dynamic Scheduling in Manufacturing Systems,” J. Sched., Vol.12, pp. 417-431, 2009.
  2. [2] I. M. Ovacik and R. Uzsoy, “Decomposition Methods for Scheduling Semiconductor Testing Facilities,” The Int. J. of Flexible Manufacturing Systems, Vol.8, pp. 357-388, 1996.
  3. [3] Y. Shen and R. C. Leachman, “Stochastic Wafer Fabrication Scheduling,” IEEE Tran. Semiconductor Manufacturing. Vol.16, No.1, pp. 2-14, 2003.
  4. [4] J.-Z. Wu and C.-F. Chien, “Modeling Semiconductor Testing Job Scheduling and Dynamic Testing Machine Configuration,” Expert Systems with Applications, Vol.35, pp. 485-496, 2008.
  5. [5] J. H. Holland. “Escaping Brittleness: The Possibilities of General Purpose Learning Algorithms Applied to Parallel Rule-based System,” Machine Learning: An Artificial Intelligence Approach, Vol.2, Morgan Kaufmann, Los Altos, pp. 593-623, 1986.
  6. [6] S. F. Smith, “Flexible learning of problem solving heuristics through adaptive search,” Proc. 8th Int. Joint Conf. on Artificial Intelligence, Vol.1, pp. 422-425, 1983.
  7. [7] K. Sakakibara, “Research about Scheduling Rule Acquisition Based on Genetic Based Machine Learning,” Doctor Thesis, Graduate School of Science and Technology, Kobe University, 2004.
  8. [8] Z. Michalewicz, “PPGenetic Algorithms + Data Structures = Evolution Programs,” Third, Revised and Extended Edition, Springer, Berlin, 1998.

Creative Commons License  This article is published under a Creative Commons Attribution-NoDerivatives 4.0 Internationa License.

*This site is desgined based on HTML5 and CSS3 for modern browsers, e.g. Chrome, Firefox, Safari, Edge, Opera.

Last updated on Dec. 06, 2024