JACIII Vol.11 No.2 pp. 168-175
doi: 10.20965/jaciii.2007.p0168


Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption

Masaya Yoshikawa and Hidekazu Terai

Department of VLSI System Design, Ritsumeikan University, 1-1-1 Nojihigashi, Kusatsu, Shiga 525-8577, Japan

November 24, 2005
August 2, 2006
February 20, 2007
genetic algorithm, low power consumption, hierarchical parallel processing, VLSI layout design
With portable information devices now widely disseminated, low power consumption LSIs are increasingly needed in battery, implementation, and heat generation applications. We propose parallel placement to realize low power consumption and confirm its effectiveness in experiments with a commercial electronic design automation (EDA) tool for designing LSIs. Our proposal hierarchically combines outline and detail placement based on genetic algorithm. In selection operators, new evaluation functions are introduced for realizing the reduction of power consumption focusing on the signal transition probability. Considering a parallel processing, in which a processing speed has a scalable relation with the number of processors, and by implementing it in a parallel computer, its effect is demonstrated.
Cite this article as:
M. Yoshikawa and H. Terai, “Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption,” J. Adv. Comput. Intell. Intell. Inform., Vol.11 No.2, pp. 168-175, 2007.
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