A Speedup Algorithm for Repetition of Hypothetical Reasoning
Haruhiko Kimura*, Tadanobu Misawa**, Koji Abe***,
and Yasuhiro Ogoshi****
*Dept. of Information and System Engineering, Kanazawa University, Kakumamachi, Kanazawa 920-1192, Japan
**School of Management, Tokyo University of Science, 500 Shimokiyoku, Kuki, Saitama 346-8512, Japan
***Dept. of Information and Computer Science, Kanazawa Institute of Technology, 7-1 Ohgigaoka, Nonoichi, Ishikawa 921-8501, Japan
****Faculty of Engineering, Fukui University, 3-9-1 Bunkyo, Fukui 910-8507, Japan
This paper presents performance evaluations of a speedup method for hypothetical reasoning to a first-order predicate logic knowledge base in the case when reasoning is executed repeatedly replacing hypothetical knowledge and keeping background knowledge and the goal intact. The proposed method consists of substituting hypotheses for predicate knowledge which has recursive structures, deriving bit patterns of solutions from background knowledge and the goal in advance when all the hypotheses are true, and finding actual solutions from inclusion relation with bit patterns of hypothetical knowledge.
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