JACIII Vol.10 No.1 pp. 112-120
doi: 10.20965/jaciii.2006.p0112


Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation

Masaya Yoshikawa, and Hidekazu Terai

Department of VLSI System Design, Ritsumeikan University, 1-1-1 Nojihigashi, Kusatsu, Shiga 525-8577, Japan

June 24, 2005
October 7, 2005
January 20, 2006
Genetic Algorithm, floorplanning, dedicated hardware, evolutionary pipeline, sequence pair
The floorplanning problem, a basic design step in layout design of very large-scale integrated circuit (VLSI), deals with placing rectangular modules at maximum density. Many studies have dealt with conducted this problem using sequence pairs based on genetic algorithms (GAs), but this generally requires much calculation time. We propose an architecture for high-speed floorplanning using a sequence pair based on GA. The proposed architecture, implemented on the field-programmable gate array (FPGA), achieves high-speed processing. Measurement evaluating the proposed architecture demonstrated speeds 37.1 times greater than software processing.
Cite this article as:
M. Yoshikawa and H. Terai, “Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation,” J. Adv. Comput. Intell. Intell. Inform., Vol.10 No.1, pp. 112-120, 2006.
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