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JACIII Vol.8 No.5 pp. 507-513
doi: 10.20965/jaciii.2004.p0507
(2004)

Paper:

Evolutionary Design of Combinational Logic Circuits

Cecília Reis*, J. A. Tenreiro Machado*, and J. Boaventura Cunha**

*Institute of Engineering of Porto, Polytechnic Institute of Porto, Rua Dr. António Bernardino de Almeida, 4200-072 Porto, Portugal

**University of Trás-os-Montes and Alto Douro, Engineering Department Apt. 1013, 5000-911 Vila Real, Portugal

Received:
August 31, 2003
Accepted:
April 20, 2004
Published:
September 20, 2004
Keywords:
circuit design, combinational circuits, genetic algorithms, computer-aided design
Abstract

This paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: 2-to-1 multiplexer, one-bit full adder, four-bit parity checker and a two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates.

Cite this article as:
Cecília Reis, J. A. Tenreiro Machado, and J. Boaventura Cunha, “Evolutionary Design of Combinational Logic Circuits,” J. Adv. Comput. Intell. Intell. Inform., Vol.8, No.5, pp. 507-513, 2004.
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Last updated on Jun. 22, 2021