Optimization of Double-Sided Polishing Conditions to Achieve High Flatness: Consideration of Relative Motion Direction

Kenji Hirose; Toshiyuki Enomoto

doi:10.20965/ijat.2009.p0581

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IJAT Vol.3 No.5 pp. 581-591

doi: 10.20965/ijat.2009.p0581

(2009)

Paper:

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Optimization of Double-Sided Polishing Conditions to Achieve High Flatness: Consideration of Relative Motion Direction

Kenji Hirose and Toshiyuki Enomoto

Department of Mechanical Engineering, Graduate School of Engineering, Osaka University, 2-1 Yamada-oka, Suita, Osaka 565-0871, Japan

Received:

March 16, 2009

Accepted:

August 3, 2009

Published:

September 5, 2009

Keywords:

double-sided polishing, flatness, tool wear, engineering optimization, silicon wafer

Abstract

Silicon (Si) wafers are the most commonly used substrates of semiconductor devices. The device design rule is miniaturization, and the device chip size is being increased to improve device integration, requiring that Si wafers be manufactured with higher flatness and larger diameters. The polishing used as a finishing process of Si wafers, however, has a serious problem; it is very difficult to set the appropriate conditions for polishing the Si wafer while wearing the polishing pad stably to high flatness. In our previous work, a method of optimizing polishing conditions based on kinematical analysis was proposed to achieve high flatness of the wafer and pad. The method, however, did not consider the effect of the relative motion direction between the wafer and the pads as an important factor in polishing behaviors. Therefore, in this study, an optimization method considering the relative motion direction is newly developed, and a series of double-sided polishings of silicon wafers shows that the wafer flatness calculated by the method corresponds well with that in the polishing experiments. Furthermore, to make the distribution of pad wear more uniform, the optimization of polishing conditions, including the wafer carrier specifications, is conducted, and the feasibility is clarified.

Cite this article as:

K. Hirose and T. Enomoto, “Optimization of Double-Sided Polishing Conditions to Achieve High Flatness: Consideration of Relative Motion Direction,” Int. J. Automation Technol., Vol.3 No.5, pp. 581-591, 2009.

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References

[1] “International Technology Roadmap for Semiconductors 2007 Edition,” Executive Summary Final Draft, p. 77, Dec. 2007.
[2] Y. Nakagawa, “Optimization of Double Sided Polishing Conditions in order to Unify Friction Distance Distribution in a Wafer,” Journal of the Japan Society for Precision Engineering, Vol.72, No.5, pp. 641-646, 2006 (in Japanese).
[3] E. Uhlmann and T. Ardelt, “Influence of Kinematics on the Face Grinding Process on Lapping Machines,” Annals of the CIRP, No.48, No.1, pp. 281-284, 1999.
[4] H. Arai, “Planarization Polishing Technique for Large Diameter of Bare Silicon Wafer,” Journal of the Japan Society for Precision Engineering, Vol.73, No.7, pp. 756-759, 2007 (in Japanese).
[5] K. Hirose and T. Enomoto, “Achievement of High Flatness of Large Diameter Silicon Wafer in Double-Sided Polishing - Optimization of Polishing Conditions Based on Kinematical Analysis -,” Transactions of the Japan Society of Mechanical Engineers, Vol.74, No 746C, pp. 267-272, 2008 (in Japanese).
[6] K. Abe, “Study for Lapping Technology of 400 mm diameter wafers - 3rd report -,” Proc. of Spring Conf. of the Japan Society for Precision Engineering, p. 566, 1998 (in Japanese).
[7] L. Xiao, B. -G. Rosen, and N. Amini, “Surface lay effect on rough friction in roller contact,” Wear, 257, pp. 1301-1307, 2004.

This article is published under a Creative Commons Attribution-NoDerivatives 4.0 Internationa License.

[1] [1] “International Technology Roadmap for Semiconductors 2007 Edition,” Executive Summary Final Draft, p. 77, Dec. 2007.

[2] [2] Y. Nakagawa, “Optimization of Double Sided Polishing Conditions in order to Unify Friction Distance Distribution in a Wafer,” Journal of the Japan Society for Precision Engineering, Vol.72, No.5, pp. 641-646, 2006 (in Japanese).

[3] [3] E. Uhlmann and T. Ardelt, “Influence of Kinematics on the Face Grinding Process on Lapping Machines,” Annals of the CIRP, No.48, No.1, pp. 281-284, 1999.

[4] [4] H. Arai, “Planarization Polishing Technique for Large Diameter of Bare Silicon Wafer,” Journal of the Japan Society for Precision Engineering, Vol.73, No.7, pp. 756-759, 2007 (in Japanese).

[5] [5] K. Hirose and T. Enomoto, “Achievement of High Flatness of Large Diameter Silicon Wafer in Double-Sided Polishing - Optimization of Polishing Conditions Based on Kinematical Analysis -,” Transactions of the Japan Society of Mechanical Engineers, Vol.74, No 746C, pp. 267-272, 2008 (in Japanese).

[6] [6] K. Abe, “Study for Lapping Technology of 400 mm diameter wafers - 3rd report -,” Proc. of Spring Conf. of the Japan Society for Precision Engineering, p. 566, 1998 (in Japanese).

[7] [7] L. Xiao, B. -G. Rosen, and N. Amini, “Surface lay effect on rough friction in roller contact,” Wear, 257, pp. 1301-1307, 2004.