Development of Image Recognition Processor Based on Configurable Processor
Takashi Miyamori*, Jun Tanabe*, Yasuhiro Taniguchi**,
Kenji Furukawa**, Tatsuo Kozakaya**, Hiroaki Nakai**,
Yukimasa Miyamoto*, Ken-ichi Maeda**,
and Masataka Matsui*
*SoC Research & Development Center, Semiconductor Company, Toshiba Corporation, 580-1 Horikawa-cho, Saiwai-ku, Kawasaki 212-8520, Japan
**Corporate Research & Development Center, Toshiba Corporation, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki 212-8582, Japan
We developed an image recognition processor, “Visconti,” based on a configurable processor. Three VLIW processors that execute three instructions in parallel are integrated into a single chip with peripheral modules such as video I/Os and an SDRAM controller. Each VLIW processor has a RISC processor core and a VLIW coprocessor dedicated to image processing. The coprocessor executes SIMD instructions such as 8-parallel byte. Visconti was fabricated using 0.13μm CMOS technology, operates at 150MHz, and consumes about 1W. We present actual application examples of Visconti, onboard surveillance for automobiles and face recognition. Compared to cases in which only the processor core is used, execution speed per one processor increases about 16 times for onboard surveillance and about five times per three processors for face recognition. These applications can be processed in real time.
Kenji Furukawa, Tatsuo Kozakaya, Hiroaki Nakai,
Yukimasa Miyamoto, Ken-ichi Maeda, and
and Masataka Matsui, “Development of Image Recognition Processor Based on Configurable Processor,” J. Robot. Mechatron., Vol.17, No.4, pp. 437-446, 2005.
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