Implementation of Face Recognition Processing Using an Embedded Processor
Hiroyuki Kondo*, Masami Nakajima*, Miroslaw Bober**,
Krzysztof Kucharski***, Osamu Yamamoto*,
and Toru Shimizu****
*System Core Technology Div., Renesas Technology Corp., 4-1 Mizuhara, Itami, Hyogo 664-0005, Japan
**Information Technology Centre Europe B.V. (ITE) Visual Information Laboratory, 20 Frederick Sanger Rd, Surrey Research Park, Guildford, Surrey, GU12SE, U.K.
***Institute of Radioelectronics, Warsaw University of Technology, ul. Nowowiejeska 15/19, 00-665 Warsaw, Poland
****System Core Technology Div., Renesas Technology Corp., 5-22-2 Josuihon-cho, Kodaira, Tokyo 187-0022, Japan
Embedded processors are conventionally difficult to use in face recognition in the security and robotic fields because of the tremendous amount of processing required. We implemented face recognition processing with a multicore based embedded processor having low power consumption and high performance. The single-chip multiprocessor is manufactured using a 0.15μm process with two M32R cores, 512KB of SRAM, and peripheral circuits integrated on a single-chip. It has a power supply voltage of 1.5V, a frequency of 600MHz, and power consumption of 800mW.
-  T. Hori, “Development of Face Recognition System,” Technical Information of Hokkaido Industrial Research Institute, Vol.25, No.2, p. 7,
-  NEC Press Release, “Press Release of Face Detection/Face Matching Engine ‘Neo Face’ which implements Various System shortly and effectively using Face Recognition Technology,” Oct. 17, 2002,
-  K. Fukui et al., “Face Recognition Technology for Robot Vision,” Toshiba Review, Vol.56, No.9, 2001,
-  Renesas Technology Corp., M32R home page,
-  T. Shimizu et al., “A Multimedia 32b RISC Microprocessor with 16Mb DRAM,” Digest of Technical Papers, 1996 IEEE Int’I Solid-State Circuits Conf., pp. 216-217, San Francisco, USA, Feb., 1996.
-  Y. Nunomura et al., “M32R/D Integrating DRAM and Microprocessor,” IEEE Micro, pp. 40-48, Nov./Dec., 1997.
-  T. Shimizu, “M32Rx/D – A Single Chip Microcontroller with A High Capacity 4MB Internal DRAM,” Proc. of HotChips10, pp. 37-48, Palo Alto, USA, Aug., 1998.
-  S. Kaneko et al., “A 600MHz Single-chip Multiprocessor with 4.8GB/s Internal Shared Pipelined Bus and 512kB Internal Memory,” Digest of Technical Papers, 2003 IEEE Int’l Solid-State Circuits Conf., pp. 254-255, San Francisco, USA, Feb., 2003.
-  J. Heeb, “Next Generation Intel StrongARM Technology Overview,” Proc. of Cool Chip III, pp. 137-148, April, 2000.
-  W. Skarbek, K. Kucharski, and M. Bober, “Dual Linear Discriminant Analysis for Face Recognition,” Fundamenta Informaticae, Vol.61, No.3-4, pp. 303-334, 2004.
-  P. Viola, and M. Jones, “Robust Real-time Object Detection,” Second International Workshop on Statistical and Computational Theories of Vision – Modeling, Learning, Computing, and Sampling, Vancouver, 2001.
-  W. Skarbek, and K. Kucharski, “Image Object Localization by AdaBoost Classifier,” International Conference on Image Analysis and Recognition ICIAR, Porto, 2004.
This article is published under a Creative Commons Attribution-NoDerivatives 4.0 Internationa License.
Copyright© 2005 by Fuji Technology Press Ltd. and Japan Society of Mechanical Engineers. All right reserved.