Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture

Masanori Hariyama; Michitaka Kameyama

doi:10.20965/jrm.2000.p0521

single-rb.php

« previous

JRM Vol.12 No.5 pp. 521-526

doi: 10.20965/jrm.2000.p0521

(2000)

Paper:

Views over last 60 days: 414

Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture

Masanori Hariyama and Michitaka Kameyama

Graduate School of Information Sciences, Tohoku University, Aoba 05, Aramaki, Aoba-ku, Sendai 980, Japan

Received:

June 15, 2000

Accepted:

September 26, 2000

Published:

October 20, 2000

Keywords:

Stereo vision, Sum of absolute differences, Intelligent-integrated systems, High-level synthesis

Abstract

This article presents a stereo-matching algorithm to establish reliable correspondence between images by selecting a desirable window size for SAD (Sum of Absolute Differences) computation. In SAD computation, parallelism between pixels in a window changes depending on its window size, while parallelism between windows is predetermined by the input-image size. Based on this consideration, a window-parallel and pixel-serial architecture is proposed to achieve 100% utilization of processing elements. Performance of the VLSI processor is evaluated to be more than 10,000 times higher than that of a general-purpose processor.

Cite this article as:

Masanori Hariyama and Michitaka Kameyama, “Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture,” J. Robot. Mechatron., Vol.12, No.5, pp. 521-526, 2000.

Data files:

This article is published under a Creative Commons Attribution-NoDerivatives 4.0 Internationa License.