Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture
Masanori Hariyama and Michitaka Kameyama
Graduate School of Information Sciences, Tohoku University, Aoba 05, Aramaki, Aoba-ku, Sendai 980, Japan
This article presents a stereo-matching algorithm to establish reliable correspondence between images by selecting a desirable window size for SAD (Sum of Absolute Differences) computation. In SAD computation, parallelism between pixels in a window changes depending on its window size, while parallelism between windows is predetermined by the input-image size. Based on this consideration, a window-parallel and pixel-serial architecture is proposed to achieve 100% utilization of processing elements. Performance of the VLSI processor is evaluated to be more than 10,000 times higher than that of a general-purpose processor.
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