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Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure
Michitaka Kameyama and Masayuki Sasaki
Department of Computer and Mathematical Sciences, graduate School of Information Sciences, Tohoku University, Aoba, Aramaki, Aoba-ku, Sendai, 980-77 Japan
Received:October 23, 1996Accepted:November 11, 1996Published:December 20, 1996
Keywords:Intelligent integrated systems, Spatially parallel processing, Temporally parallel processing, Mini mum delay time, Scheduling
Abstract
In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to the change of the environment very quickly. Therefore, the development of special-purpose VLSI processors with minimum delay time becomes a very important subject. A suitable combination of spatially parallel and temporally parallel processing is very important to realize the minimum delay time. In this article, we present a scheduling algorithm for high-level synthesis, where the input to the scheduler is a behavioral description viewed as a data flow graph. The scheduler minimizes the delay time under the constraint of a silicon area and I/O pins.
Cite this article as:M. Kameyama and M. Sasaki, “Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure,” J. Robot. Mechatron., Vol.8 No.6, pp. 516-523, 1996.Data files:
