Top > JACIII > Comparison of Knowledge Acquisition Methods for Dynamic Schedu ...

single-jc.php

JACIII Vol.19 No.1 pp. 58-66
doi: 10.20965/jaciii.2015.p0058
(2015)

Paper:

Views over last 60 days: 881

Comparison of Knowledge Acquisition Methods for Dynamic Scheduling of Wafer Test Processes with Unpredictable Testing Errors

Tsubasa Matsuo*, Masahiro Inuiguchi*, and Kenichiro Masunaga**

*Graduate School of Engineering Science, Osaka University, 1-3 Machikaneyama, Toyonaka, Osaka 560-8531, Japan

**Renesas Electronics Co., 2-6-2 Otemachi, Chiyoda-ku, Tokyo 100-0004, Japan

Received:
April 20, 2014
Accepted:
August 25, 2014
Published:
January 20, 2015
Creative Commons License
Keywords:
semiconductor manufacturing, simulation, genetic-based machine learning
Abstract
The scheduling of semiconductor wafer testing processes may be seen as a resource constraint project scheduling problem (RCPSP), but it includes uncertainties caused by wafer error, human factors, etc. Because uncertainties are not simply quantitative, estimating the range of the parameters is not useful. Considering such uncertainties, finding a good situationdependent dispatching rule is more suitable than solving an RCPSP under uncertainties. In this paper we apply machine learning approaches to acquiring situation-dependent dispatching rule. We compare obtained rules and examine their effectiveness and usefulness in problems with unpredictable wafer testing errors.
Cite this article as:
T. Matsuo, M. Inuiguchi, and K. Masunaga, “Comparison of Knowledge Acquisition Methods for Dynamic Scheduling of Wafer Test Processes with Unpredictable Testing Errors,” J. Adv. Comput. Intell. Intell. Inform., Vol.19 No.1, pp. 58-66, 2015.
Data files:
References
  1. [1] D. Ouelhadj and S. Petrovic, “A Survey of Dynamic Scheduling in Manufacturing Systems,” J. Sched., Vo.12, pp. 417-431, 2009.
  2. [2] I.M. Ovacik and R. Uzsoy,” “Decomposition Methods for Scheduling Semiconductor Testing Facilities,” The Int. J. of Flexible Manufacturing Systems, Vol.8, pp. 357-388, 1996.
  3. [3] Y. Shen and R. C. Leachman, “Stochastic Wafer Fabrication Scheduling,” IEEE Tran. Semiconductor Manufacturing, Vol.16, No.1, pp. 2-14, 2003.
  4. [4] J.-Z. Wu and C.-F. Chien, “Modeling Semiconductor Testing Job Scheduling and Dynamic Testing Machine Configuration,” Expert Systems with Applications, Vol.35, pp. 485-496, 2008.
  5. [5] Z. Michalewicz, “Genetic Algorithms + Data Structures = Evolution Programs,” 3rd, Revised and Extended Ed., Springer, Berlin, 1998.
  6. [6] T. Matsuo, M. Inuiguchi, K. Masunaga, and D. Hirota, “Dynamic Scheduling Approaches to Wafer Test Scheduling with Unpredictable Error,” J. of Advanced Computational Intelligence and Intelligent Informatics, Vol.17, pp. 526-534, 2013.
  7. [7] S. F. Smith, “Flexible learning of problem solving heuristics through adaptive search,” Proc. 8th Int. Joint Conf. on Artificial Intelligence, Vol.1, pp. 422-425, 1983.
  8. [8] K. Sakakibara, “Research about Scheduling Rule Acquisition Based on Genetic Based Machine Learning,” Graduate School of Science and Technology, Doctor Thesis, Kobe University, 2004.
  9. [9] J. R. Quinlan, “C4.5: Programs for Machine Learning,” Morgan Kaufmann Publishers, 1993.

Creative Commons License  This article is published under a Creative Commons Attribution-NoDerivatives 4.0 Internationa License.

*This site is desgined based on HTML5 and CSS3 for modern browsers, e.g. Chrome, Firefox, Safari, Edge, Opera.

Last updated on Oct. 01, 2024