Paper:
Characterization of Multiple-Valued Logic for Dealing with Ambiguity
Noboru Takagi
Department of Intelligent Systems Design Engineering, Toyama Prefectural University, 5180 Kurokawa Imizu-shi, Toyama 939-0398, Japan
- [1] S. C. Kleene, “Introduction to Metamathematics,” North-Holland Pub., pp. 332-340, 1952.
- [2] M. Mukaidono, “Regular Ternary Logic Functions – Ternary Logic Functions Suitable for Treating Ambiguity,” IEEE Trans. on Computers, Vol.C-35, No.2, pp. 179-183, 1986.
- [3] M. Mukaidono, “On the Mathematical Structure of the C-type Fail Safe Logic,” IECE Trans., Vol.52-C, No.12, pp. 812-819, 1969.
- [4] M. Mukaidono, “The B-ternary logic and its application to the detection of hazards in combinational switching circuits,” Proc. of the 8th Int. Symposium on Multiple-Valued Logic, IEEE, pp. 269-275, 1978.
- [5] Y. Yamamoto and M. Mukaidono, “P-functions – ternary logic functions capable of correcting input failures and suitable for treating ambiguities,” IEEE Trans. on Computers, Vol.41, No.1, pp. 28-35, 1992.
- [6] M. Mukaidono and I. G. Rosenberg, “k-valued Function for Treating Ambiguities – Their Clone and a Normal Form,” Proc. of the 16th Int. Symposium onMultiple-Valued Logic, IEEE, pp. 204-211, 1986.
- [7] I. G. Rosenberg, “Completeness properties of multiple-valued logic algebras,” D. C. Rine (Ed.), Computer Science and Multiple-Valued Logic, North-Holland, pp. 150-192, 1984.
- [8] E. L. Post, “Introduction to a general theory of elementary propositions,” American J. of Mathematics, Vol.43, pp. 163-185, 1921.
- [9] K. Ibuki, K. Naemura, and A. Nozaki, “The general theory of complete sets of logical functions,” IECE Trans., Vol.46, No.7, pp. 42-48, 1963.
- [10] J. C. Muzio and T. C. Wesselkamper, “Multiple-Valued Switching Theory,” Adam Hilger Ltd., pp. 63-100, 1986.
- [11] G. Epstein, “Multiple-Valued Logic Design: An Introduction,” Institute of Physics Publishing, pp. 124-153, 1993.
- [12] J. A. Brzozowski and C. H. Seger, “Asynchronous Circuits,” Springer-Verlag, 1995.
- [13] J. A. Brzozowski and Z. Esik, “Hazard algebras,” Formal Methods in System Design, Vol.23, Issue 3, pp. 233-256, 2003.
- [14] N. Takagi, “A delay model of multiple-valued logic circuits consisting of min, max, and literal operations,” IEICE Trans. on Information and Systems, Vol.E93-D, No.8, pp. 2040-2047, 2010.
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