JACIII Vol.10 No.6 pp. 931-938
doi: 10.20965/jaciii.2006.p0931


An Efficient Specification for System Verification

Chikatoshi Yamada*, Yasunori Nagata**, and Zensho Nakao**

*Takushoku University Hokkaido College, 4558 Memu, Fukagawa, Hokkaido 074-8585, Japan

**Department of Electrical and Electronics Engineering, University of the Ryukyus, 1 Senbaru, Nishihara, Nakagami, Okinawa 903-0213, Japan

November 11, 2005
February 8, 2006
November 20, 2006
formal verification, computation tree logic, temporal formula specification, strong/weak temporal order relation
In design of complex and large scale systems, system verification has played an important role. In this article, we focus on specification process of model checking in system verifications. Modeled systems are in general specified by temporal formulas of computation tree logic, and users must know well about temporal specification because the specification might be complex. We propose a method by which specifications with temporal formulas are obtained inductively. We will show verification results using the proposed temporal formula specification method, and show that amount of memory, OBDD nodes, and execution time are reduced.
Cite this article as:
C. Yamada, Y. Nagata, and Z. Nakao, “An Efficient Specification for System Verification,” J. Adv. Comput. Intell. Intell. Inform., Vol.10 No.6, pp. 931-938, 2006.
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Last updated on Apr. 05, 2024