single-jc.php

JACIII Vol.4 No.5 pp. 380-386
doi: 10.20965/jaciii.2000.p0380
(2000)

Paper:

Fuzzy Flip-Flops and their Applications to Fuzzy Memory Element and Circuit Design using FPGA

Shin-ichi Yoshida, Yasufumi Takama and Kaoru Hirota

Deptartment of Computational Intelligence and Systems Science
Interdisciplinary Graduate School of Science and Engineering Tokyo Institute of Technology 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8502, Japan

Received:
September 29,
Accepted:
October 16, 2000
Published:
September 20, 2000
Keywords:
Fuzzy flip-flop, Memory element, Fuzzy logic, FPGA, Logic circuit
Abstract

D, T, and SR fuzzy flip-flops are proposed and their characteristics are shown in four – max-min, algebraic, bounded, drastic – logical operation systems. The circuits of the proposed flip-flops are designed and simulated on a Synopsys circuit simulator. The result of synthesis show the areas of D, T, SR fuzzy flip-flops are nearly 0, 2/3 1/2 of that of conventional JK fuzzy flip-flops and the delay times of D, T, SR fuzzy flip-flops are nearly 0, 2/3, 2/3 of that of the JK type. Moreover, max-min fuzzy memory element based on functions required for memory is proposed independently of fuzzy flip-flops. As it uses 1/2 circuit area of the SR fuzzy flip-flops, it is more suitable for fuzzy memory element than other fuzzy flipflops.

Cite this article as:
Shin-ichi Yoshida, Yasufumi Takama, and Kaoru Hirota, “Fuzzy Flip-Flops and their Applications to Fuzzy Memory Element and Circuit Design using FPGA,” J. Adv. Comput. Intell. Intell. Inform., Vol.4, No.5, pp. 380-386, 2000.
Data files:

*This site is desgined based on HTML5 and CSS3 for modern browsers, e.g. Chrome, Firefox, Safari, Edge, Opera.

Last updated on May. 04, 2021