Fuzzy Flip-Flops and their Applications to Fuzzy Memory Element and Circuit Design using FPGA
Shin-ichi Yoshida, Yasufumi Takama and Kaoru Hirota
Deptartment of Computational Intelligence and Systems Science
Interdisciplinary Graduate School of Science and Engineering Tokyo Institute of Technology 4259 Nagatsuta-cho, Midori-ku, Yokohama 226-8502, Japan
D, T, and SR fuzzy flip-flops are proposed and their characteristics are shown in four – max-min, algebraic, bounded, drastic – logical operation systems. The circuits of the proposed flip-flops are designed and simulated on a Synopsys circuit simulator. The result of synthesis show the areas of D, T, SR fuzzy flip-flops are nearly 0, 2/3 1/2 of that of conventional JK fuzzy flip-flops and the delay times of D, T, SR fuzzy flip-flops are nearly 0, 2/3, 2/3 of that of the JK type. Moreover, max-min fuzzy memory element based on functions required for memory is proposed independently of fuzzy flip-flops. As it uses 1/2 circuit area of the SR fuzzy flip-flops, it is more suitable for fuzzy memory element than other fuzzy flipflops.
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