JRM Vol.6 No.2 pp. 137-142
doi: 10.20965/jrm.1994.p0137


Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles

Masanori Hariyama and Michitaka Kameyama

Department of Computer and Mathematical Sciences, Graduate School of Information Sciences, Tohoku University, Aoba, Aramaki, Aoba-ku, Sendai, Miyagi, 980-77 Japan

November 14, 1993
November 28, 1993
April 20, 1994
Special-purpose, VLSI, Collision avoidance, Content- adressable memory, Rectangular solid representation
Since careless driving causes a terrible traffic accident, it is an important subject for a vehicle to avoid collision autonomously. Real-time collision detection between a vehicle and an obstacle will be a key target for the nextgeneration car electronics system. In collision detection, high-computational power is essential not only in coordinate transformation but also in matching operation. In the proposed collision detection VLSI processor, the matching operation is sharply accelerated by using a content-addressable memory which evaluates the magnitude relationships between an input word and all the stored words in parallel. Parallel architecture using several identical processor elements (PEs) is employed to perform the coordinate transformation at high speeds, and each PE performs coordinate transformation at high speeds based on the Coordinate Rotation Digital Computation (CORDIC) algorithms. When the 16 PEs and 144-kb CAM are used, the performance is evaluated to be 6.48ms.
Cite this article as:
M. Hariyama and M. Kameyama, “Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles,” J. Robot. Mechatron., Vol.6 No.2, pp. 137-142, 1994.
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