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Journal of Robotics and Mechatronics

ISSN : 0915-3942(Print) / 1883-8049(Online)
Editor-in-Chief :Tatsuo Arai(Osaka University)
Deputy Editor-in-Chief :Kazuhiro Kosuge (Tohoku University), Yasuhisa Hasegawa (University of Tsukuba)
Technically Co-sponsored by Robotics and Mechatronics Division of Japan Society of Mechanical Engineers

JRM Vol.17 No.4 Aug. 2005

Special Issue on VLSI Computing for Real-World Intelligent Systems: Editor: Masanori Hariyama (Graduate School of Information Scinece, Tohoku University)

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JRM Vol.17 No.4 Aug. 2005

Editorial:

Special Issue on VLSI Computing for Real-World Intelligent Systems

Masanori Hariyama, pp. 371

Recently, intelligent systems are desired to support human in real world such as advanced safe vehicles, home service robots, wearable computing devices, and intelligent home security systems. Such intelligent systems require extremely high computational power that exceeds that of state-of-the-art microprocessors. They also require

Low power consumption

Low latency from input to output

Compactness

Special-purpose processors called "system LSIs" play an essential role in meeting these requirements. This special issue focuses on the latest advances in system LSIs for real-world intelligent systems. One of their most important tasks is sensing environmental information such as visual information. Image and angle sensors, for example, are implemented in system LSIs. Image processing is the most time-consuming in real-world intelligent systems due to the extremely large amount of data. To overcome this problem, novel parallel architectures are presented. Electrical wires between processing modules must be minimized to make intelligent systems compact. High-speed serial data transfer is one most effective way to minimize the electrical wires. An architecture that handles processing order based on task priorities is a key to low latency. Processing of human interfaces such as face detection and speech recognition are also important factors in making intelligent systems user-friendly.

I thank the authors of the articles in this issue for their effort and contributions, and the members of the Editorial Board for their cooperation.

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Paper:: A Digital Vision Chip for Early Feature Extraction with Rotated Template-Matching CA; Masayuki Ikebe, and Tetsuya Asai, pp. 372-377; Abstract | Preview | Full Text (PDF481KB)
Paper:: A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation; Teppei Nakano, Takashi Morie, Makoto Nagata, and Atsushi Iwata, pp. 378-386; Abstract | Preview | Full Text (PDF811KB)
Paper:: A Pixel-Parallel Algorithm for Detecting and Tracking Fast-Moving Modulated Light Signals; Shingo Kagami, Masatsugu Shinmeimae, Takashi Komuro, Yoshihiro Watanabe, and Masatoshi Ishikawa, pp. 387-394; Abstract | Preview | Full Text (PDF243KB)
Paper:: A 3.7×3.7mm² 310.9mW 105.2msec 512×512-Pixel Phase-Only Correlation Processor; Naoto Miyamoto, Koji Kotani, and Tadahiro Ohmi, pp. 395-400; Abstract | Preview | Full Text (PDF457KB)
Paper:: Realtime FPGA-Based Vision System; Shinichi Hirai, Masakazu Zakoji, Akihiro Masubuchi, and Tatsuhiko Tsuboi, pp. 401-409; Abstract | Preview | Full Text (PDF313KB)

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Paper:: Real-Time Shape Recognition Using a Pixel-Parallel Processor; Takashi Komuro, Yoshiki Senjo, Kiyohiro Sogen, Shingo Kagami, and Masatoshi Ishikawa, pp. 410-419; Abstract | Preview | Full Text (PDF531KB)
Paper:: Parallel Extraction Architecture for Information of Numerous Particles in Real-Time Image Measurement; Yoshihiro Watanabe, Takashi Komuro, Shingo Kagami, and Masatoshi Ishikawa, pp. 420-427; Abstract | Preview | Full Text (PDF277KB)
Paper:: Implementation of Face Recognition Processing Using an Embedded Processor; Hiroyuki Kondo, Masami Nakajima, Miroslaw Bober, Krzysztof Kucharski, Osamu Yamamoto, and Toru Shimizu, pp. 428-436; Abstract | Preview | Full Text (PDF456KB)
Paper:: Development of Image Recognition Processor Based on Configurable Processor; Takashi Miyamori, Jun Tanabe, Yasuhiro Taniguchi, Kenji Furukawa, Tatsuo Kozakaya, Hiroaki Nakai, Yukimasa Miyamoto, Ken-ichi Maeda, and Masataka Matsui, pp. 437-446; Abstract | Preview | Full Text (PDF609KB)
Paper:: VLSI Architecture for Robust Speech Recognition Systems and its Implementation on a Verification Platform; Shingo Yoshizawa, Noboru Hayasaka, Naoya Wada, and Yoshikazu Miyanaga, pp. 447-455; Abstract | Preview | Full Text (PDF328KB)

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Paper:: Design and Implementation of the Multimedia Operation Mechanism for Responsive Multithreaded Processor; Tsutomu Itou, and Nobuyuki Yamasaki, pp. 456-462; Abstract | Preview | Full Text (PDF334KB)
Paper:: A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors; Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, and Atsushi Iwata, pp. 463-468; Abstract | Preview | Full Text (PDF488KB)
Paper:: Angle Detection Methods for a CMOS Smart Rotary Encoder; Kazuhiro Nakano, Toru Takahashi, and Shoji Kawahito, pp. 469-474; Abstract | Preview | Full Text (PDF138KB)
Paper:: Field Emission of Individual Carbon Nanotubes and its Improvement by Decoration with Ruthenium Dioxide Super-Nanoparticles; Pou Liu, Fumihito Arai, Lixin Dong, Toshio Fukuda, Tsuneyuki Noguchi, and Katsuyoshi Tatenuma, pp. 475-482; Abstract | Preview | Full Text (PDF492KB)
Paper:: Polynomial Linear Quadratic Gaussian and Sliding Mode Observer for a Quadrotor Unmanned Aerial Vehicle; Abdellah Mokhtari, Abdelaziz Benallegue, and Abdelkader Belaidi, pp. 483-495; Abstract | Preview | Full Text (PDF770KB)

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